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Microelectronics devices contain many electronic components within an active
silicon chip, such as transistors, capacitors, resistors, etc. To form a
usable device, a silicon chip requires protection from the environment as well
as both electrical and mechanical connections to the surrounding components.
The technology dealing with these requirements is called electronic packaging.
The physical design of an electronic package starts from the functions of the
integrated circuits on the semiconductor chips and components. The design must
provide access to all the terminals on the chips for input power and signal
transmission. Secondly the design must provide the electrical wiring for
interconnection. In addition, thermal energy transformed from electrical energy
must be dissipated, and all the circuits must be protected from damage during
next level assembly and its service life.
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An electronic package is comprised of various conducting and insulating materials,
which have different coefficients of thermal expansions (CTE). Figure 1 illustrates
a cross-sectional view of a multi-chip ceramic ball grid array (CBGA) package
assembly, where a silicon chip is mounted on a multi-layer ceramic module and the
module is attached to a printed circuit board (PCB) through solder ball
interconnections to form a final second level assembly. In addition, a metal heat
sink is attached to the module to dissipate the excessive heat. The bold numbers
shown in Fig. 1 indicate a typical CTE value of each material in ppm/C. When the
chip is powered up so that the package is subjected to a temperature change, each
material deforms at a different rate. This non-uniform CTE distribution produces
thermally induced mechanical stresses within the package assembly.
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| Fig. 1: CTE distribution of a typical CBGA package assembly |
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The thermal deformations are induced by (1) a global CTE mismatch between the module
and PCB and (2) a local CTE mismatch between the adjacent materials at the interfaces.
The effect of global CTE mismatch is illustrated in Fig. 2a.
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| Fig. 2a: Global CTE mismatch |
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When the assembly is cooled from an assembly temperature, the PCB contracts more than the module. This uneven
contraction produces a global bending of the whole assembly as well as relative
horizontal displacements between the top and bottom of solder balls. The effect of local
CTE mismatch on a solder ball deformation is illustrated in Fig. 2b, where the dashed line
indicates an original shape of solder joint at the reflow temperature. When it is cooled
to room temperature, the free thermal contraction of the solder joint at the interfaces
are constrained by adjacent materials which have a lower CTE.
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| Fig. 2b: Local CTE mismatch |
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In general, if the global effect reinforces the local effect at a point in the package,
the concentrated strain will be accumulated during thermal cycles, which would result in
the premature failure of the device during operation. Figure 3 shows the cross section
of the leftmost solder ball of a CBGA package assembly before and after an accelerated
thermal cycling (ATC) test. The relative horizontal displacements and fatigue cracks in
the failed solder ball are evident.
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| Fig 3: Cross section of CBGA package assembly before(left) and after(right) ATC test |
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The traditional role of mechanical analysis in electronic packaging was reliability
assessment of microelectronics devices at the final stage of development. The shrinking
product development cycle time, however, has changed the role of mechanical analysis from
a problem solving (passive) mode to a predictive (active) mode, where the mechanical
analysis is performed for (1) performance optimization and (2) reliability prediction of
a new technology product at its conceptual stage of development. This dependency of
product development on mechanical analysis has fostered increasing activity in mechanical
experimentation, both for specific studies and for guidance of numerical modeling.
As the components and structures involved in high-end microelectronics devices are made
smaller, the thermal gradient increases and the strain concentrations become more serious.
Numerical analyses have been used extensively to estimate stresses and strains in packaging
structures. Although one can model almost any kind of microelectronics device for complex
loading and boundary conditions, simplification and uncertainties are inevitable. The
models and results usually require verification by other means. Accordingly, advanced
experimental techniques are in high demand to provide accurate solutions for deformation
studies of microelectronics devices.
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