Introduction

Rapid growth in several key technological areas such as communications, transportation, computers, software and consumer electronics has been possible due to tremendous advances in the integrated circuit manufacturing technology. In the last 25 years, the semiconductor industry has grown from the Intel 4004 chip containing 2300 transistors to the 9.3 million transistors of Digital 21164 closely following Moore’s Law. This has been possible due to the equally rapid advancements in manufacturing process and IC design technology. Increasing demands for more powerful and smaller computing machines have fueled the need to manufacture such complex ICs. It is predicted that this need of the electronic industry for even more complex ICs is  going to grow at an even faster rate. By the end of this century a state-of-the-art microprocessor may be expected to contain upwards of about 50 million transistors.

    From a cost point of view, such a growth was unhindered in the past mainly because manufacturers were able to maintain sufficient volume of production to ensure low cost per fabricated unit. Increasing demand for more IC products have, however, attracted more manufacturers making very similar products resulting in a highly competitive market. At the same time, the continuous drive towards smaller feature size on an IC and larger die size itself has caused an increase in the cost of manufacturing. Tough competition and increasing cost have thus made semiconductor manufacturing a risky venture.

    To be more specific, the cost of a new VLSI fabrication line producing several different products using several hundred processing steps, is now estimated to be close to a billion dollars. Both the cost and complexity of manufacturing have been observed in the past to increase exponentially and there has been no indication that this trend is going to slow down. To maintain a competitive edge, ICs must be precisely manufactured within tight tolerances. Thus, in order to keep the cost of manufacturing down one must ensure that no errors are made during any of the stages of producing ICs from design to packaging. Manufacturing ICs without any errors is a complex task. Whenever a new process or product is introduced, the manufacturing yield or the fraction of correctly manufactured ICs is usually low. One has to ensure not only that the processes and products are designed to be high yielding but also that errors in manufacturing are eliminated as quickly as possible through continuous and timely improvements. This correction process is known as yield learning.

    Rapid yield learning is key to manufacturing success. High yield not only translates to lower cost per unit but also means that a larger number of ICs can be delivered in time to maintain a competitive edge. Therefore, one must be able to ramp up yield quickly using available resources efficiently. The rate of yield learning is a function of a number of inter-dependent attributes of IC design, fabrication process and the failure analysis facility. These attributes in turn depend on a large number of possible choices related to design style, products, equipment, technology, etc. Therefore, the technology to debug the manufacturing line needs to be more complex and advanced than the product technology to be effective and, hence, very costly. Optimum exploration of cost-revenue trade-offs requires adequate simulation and experimental models to be developed taking into consideration the yield learning process. Examples of rapid yield learning, which are dealt with in this report are SSA (Spatial Signature Analysis) and the use of information theory to improve knowledge extraction rate.